<aside> 🧑🏻‍💻 After graduating in 2017, I joined SSIR as a Senior Engineer in the Digital IP Development Team (part of Samsung's B2B Foundry division) and was involved in the RTL design of several cryptographic IPs, digital blocks of high-speed transceiver IPs, and test chips.

I had an incredible experience contributing to these cutting-edge products and collaborating with an amazing group of people. I also had the chance to utilize my creative side to plan and organize many of the fun events at SSIR that made this experience even more enjoyable.

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Job Roles

Associate Staff Engineer

Cryptographic Accelerator IP Design Team

Mar. 2020 - Aug. 2021

(1 year 6 months)

Developed encryption, hashing, and authenticated encryption IPs for Samsung’s security solutions. Demonstrated the feasibility and advantages of employing SystemC-based HLS for developing crypto IPs.

Took complete ownership of IP designs that involved,

• devising micro-architectures to achieve target objectives
• writing optimal Verilog/HLS codes
• creating sanity test benches
• running simulations and debugging waveforms
• performing design quality checks (Lint, LEC, XPROP, IPXACT, etc.)
• developing constraints for netlist synthesis
• analyzing timing reports
• supporting DV for coverage closures and
• drafting high-quality design documents and presentations

<aside> ©️ For one of the crypto IPs based on ZUC, I implemented novel techniques to significantly reduce the critical path delays compared to the reference design along with doubling of throughput for one of the modes of operation. These results were above and beyond the target requirements and also led to the filing of my first patent as the primary inventor.

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Senior Engineer

High-Speed SerDes PHY IP & Test Chip Design Team

Jul. 2017 - Feb. 2020

(2 years 8 months)

Started out by developing and testing unit-level blocks for display transceiver IPs and eventually worked on system-level modules such as BIST and test-chip logic.